Module bcm2711_pac::dmac::DMA_CS
source · [−]Modules
Abort DMA (W1SC)
Acitvate the DMA
Disable debug pause signal
DREQ state (RO)
DMA paused by DREQ state (RO)
DMA end flag (W1C)
DMA error (RO)
Interrupt status (W1C)
AXI panic priority level
DMA paused state (RO)
AXI priority level
DMA channel reset (W1SC)
DMA is waiting for the last write to be received (RO)
Wait for outstanding writes