Module bcm2711_pac::dmac::DMA_TI
source · [−]Modules
Burst transfer length
Control destination writes with DREQ
Ignore writes
Destination address increment
Destination transfer width
Interrupt enable
Don’t do wide writes as a two-beat burst
Peripheral mapping
Control source reads with DREQ
Ignore reads
Source address increment
Source transfer width
2D mode
Add wait cycles
Wait for a write response