Module bcm2711_pac::dmac::ENABLE

Modules

Set the 1G SDRAM ram page that the 32-bit DMA engines (DMA0-6) will access when addressing the 1G uncached range 0xc000_0000..=0xffff_ffff

Set the 1G SDRAM ram page that the DMA Lite engines (DMA7-10) will access when addressing the 1G uncached range 0xc000_0000..=0xffff_ffff

Construct a Field representing the EN bit (enable, RW) corresponding to the specified DMA engine instance.