Module bcm2711_pac::aux::AUX_SPI_CNTL0_REG
source · [−]Modules
Clear FIFOs
Invert SPI CLK
Chip selects
DOUT hold time
Enable
In rising
Out rising
Post-input mode
Shift length
SHift out MS bit first
Speed: spi_clk_freq = system_clock_freq / 2 * (speed + 1)
Variable CS
Variable width