pub enum Value {}
Expand description

Read from RX FIFO or write to TX FIFO

DMA Mode (DMAEN set): If TA is clear, the first 32-bit write to this register will control SPIDLEN and SPICS. Subsequent reads and writes will be taken as four-byte data words to be read or written to the FIFOs.

Poll/Interrupt Mode (DMAEN clear, TA set): Writes to the register write bytes to the TX FIFO. Reads from the register read bytes from the RX FIFO.

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