pub enum Value {}
Expand description
Read from RX FIFO or write to TX FIFO
DMA Mode (DMAEN
set): If TA
is clear, the first 32-bit write
to this register will control SPIDLEN
and SPICS
. Subsequent
reads and writes will be taken as four-byte data words to be read
or written to the FIFOs.
Poll/Interrupt Mode (DMAEN
clear, TA
set): Writes to the
register write bytes to the TX FIFO. Reads from the register read
bytes from the RX FIFO.
Trait Implementations
Auto Trait Implementations
impl RefUnwindSafe for Value
impl Send for Value
impl Sync for Value
impl Unpin for Value
impl UnwindSafe for Value
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more