Module bcm2711_pac::dmac::DMA4_CS
source · [−]Modules
Abort DMA (W1SC)
Activate the DMA4
Disable debug pause signal
Indicates the DMA4 is busy (RO)
DREQ state (RO)
DMA paused by DREQ state (RO)
End flag (W1C)
DMA error (RO)
Interrupt status (W1C)
Indicates that there are outstanding AXI transfers, either outstanding read data or outstanding write responses (RO)
AXI panic QoS level
AXI QoS Level
DMA read paused state (RO)
The DMA4 is waiting for all the write response to be returned (RO)
Wait for outstanding writes
DMA write paused state (RO)